There has been a clock generator in which a delay clock “rise” and a delay clock “fall” are respectively output from, for example, an N-th stage and a 2N-th stage of a delay circuit by two selectors, after which the rise delay clock and the fall delay clock are respectively divided by two by a rise flip-flop and a fall flip-flop and then an exclusive OR of the resulting two divided-by-two clocks is output by an exclusive OR circuit.
This conventional clock generator generates sampling clocks with a duty ratio of 50% that differs from a basic clock only in the phase (see Japanese Laid-open Patent Publication No. 2004-328448, for example).